`timescale 1ns/1ps
//in wrapper ,all control signals active high
// 4096*128 = 4*4096*32
module ram_dp_d4096_w128_wrapper (clka,clkb,wea,web,addra,addrb,dina,dinb,douta,doutb,ram_dp_cfg_register);
  input  clka;
  input  clkb;
  input [11:0] ram_dp_cfg_register;
  input  wea;//write enable,active high
  input  web; 
  input [11:0] addra;
  input [11:0] addrb;
  input [127:0] dina;
  input [127:0] dinb;
  output [127:0] douta;//rdata
  output [127:0] doutb;

wire [31:0]   douta0,doutb0;
wire [31:0]   dina0,dinb0;

wire [31:0]   douta1,doutb1;
wire [31:0]   dina1,dinb1;

wire [31:0]   douta2,doutb2;
wire [31:0]   dina2,dinb2;

wire [31:0]   douta3,doutb3;
wire [31:0]   dina3,dinb3;

assign dina0 = dina[31:0];
assign dina1 = dina[63:32];
assign dina2 = dina[95:64];
assign dina3 = dina[127:96];

assign dinb0 = dinb[31:0];
assign dinb1 = dinb[63:32];
assign dinb2 = dinb[95:64];
assign dinb3 = dinb[127:96];

assign douta = {douta3,douta2,douta1,douta0};
assign doutb = {doutb3,doutb2,doutb1,doutb0};

reg cena,cenb;
//wirte first
always@(*)begin
   if((addra == addrb))begin
      case({wea,web}) 
	2'b00:begin//(rd a&b) 
		cena = 1'b0;
	        cenb = 1'b0;
              end
        2'b01:begin//(read a,wirte b) ,wirt b first
		cena = 1'b1;
	        cenb = 1'b0;
              end
        2'b10:begin//(wirte a,read b) ,wirt a first
		cena = 1'b0;
	        cenb = 1'b1;
              end
        2'b11:begin//(wirte a&b) ,wirt a first
		cena = 1'b0;
	        cenb = 1'b1;
              end
	default:begin
		cena = 1'b0;
	        cenb = 1'b0;
              end
   endcase
   end
   else begin
        cena = 1'b0;
	cenb = 1'b0;
   end
end

ram_dp_d4096_w32 U0_ram_dp_d4096_w32(
.CENYA(),
.WENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(douta0),
.QB(doutb0),
.SOA(),
.SOB(),
.CLKA(clka),
.CENA(cena),
.WENA(~wea),
.AA(addra),
.DA(dina0),
.CLKB(clkb),
.CENB(cenb),
.WENB(1'b1),//~web
.AB(addrb),
.DB(dinb0),
.EMAA(ram_dp_cfg_register[11:9]),
.EMAWA(ram_dp_cfg_register[8:7]),
.EMASA(ram_dp_cfg_register[6]),
.EMAB(ram_dp_cfg_register[5:3]),
.EMAWB(ram_dp_cfg_register[2:1]),
.EMASB(ram_dp_cfg_register[0]),
.TENA(1'b1),
.TCENA(1'b1),
.TWENA(1'b1),
.TAA(12'b0),
.TDA(32'b0),
.TENB(1'b1),
.TCENB(1'b1),
.TWENB(1'b1),
.TAB(12'b0),
.TDB(32'b0),
.RET1N(1'b1),
.SIA(2'b1),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b1),
.SEB(1'b0),
.COLLDISN(1'b1) 
);

ram_dp_d4096_w32 U1_ram_dp_d4096_w32(
.CENYA(),
.WENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(douta1),
.QB(doutb1),
.SOA(),
.SOB(),
.CLKA(clka),
.CENA(cena),
.WENA(~wea),
.AA(addra),
.DA(dina1),
.CLKB(clkb),
.CENB(cenb),
.WENB(1'b1),//~web
.AB(addrb),
.DB(dinb1),
.EMAA(ram_dp_cfg_register[11:9]),
.EMAWA(ram_dp_cfg_register[8:7]),
.EMASA(ram_dp_cfg_register[6]),
.EMAB(ram_dp_cfg_register[5:3]),
.EMAWB(ram_dp_cfg_register[2:1]),
.EMASB(ram_dp_cfg_register[0]),
.TENA(1'b1),
.TCENA(1'b1),
.TWENA(1'b1),
.TAA(12'b0),
.TDA(32'b0),
.TENB(1'b1),
.TCENB(1'b1),
.TWENB(1'b1),
.TAB(12'b0),
.TDB(32'b0),
.RET1N(1'b1),
.SIA(2'b1),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b1),
.SEB(1'b0),
.COLLDISN(1'b1) 
);

ram_dp_d4096_w32 U2_ram_dp_d4096_w32(
.CENYA(),
.WENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(douta2),
.QB(doutb2),
.SOA(),
.SOB(),
.CLKA(clka),
.CENA(cena),
.WENA(~wea),
.AA(addra),
.DA(dina2),
.CLKB(clkb),
.CENB(cenb),
.WENB(1'b1),//~web
.AB(addrb),
.DB(dinb2),
.EMAA(ram_dp_cfg_register[11:9]),
.EMAWA(ram_dp_cfg_register[8:7]),
.EMASA(ram_dp_cfg_register[6]),
.EMAB(ram_dp_cfg_register[5:3]),
.EMAWB(ram_dp_cfg_register[2:1]),
.EMASB(ram_dp_cfg_register[0]),
.TENA(1'b1),
.TCENA(1'b1),
.TWENA(1'b1),
.TAA(12'b0),
.TDA(32'b0),
.TENB(1'b1),
.TCENB(1'b1),
.TWENB(1'b1),
.TAB(12'b0),
.TDB(32'b0),
.RET1N(1'b1),
.SIA(2'b1),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b1),
.SEB(1'b0),
.COLLDISN(1'b1) 
);

ram_dp_d4096_w32 U3_ram_dp_d4096_w32(
.CENYA(),
.WENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(douta3),
.QB(doutb3),
.SOA(),
.SOB(),
.CLKA(clka),
.CENA(cena),
.WENA(~wea),
.AA(addra),
.DA(dina3),
.CLKB(clkb),
.CENB(cenb),
.WENB(1'b1),//~web
.AB(addrb),
.DB(dinb3),
.EMAA(ram_dp_cfg_register[11:9]),
.EMAWA(ram_dp_cfg_register[8:7]),
.EMASA(ram_dp_cfg_register[6]),
.EMAB(ram_dp_cfg_register[5:3]),
.EMAWB(ram_dp_cfg_register[2:1]),
.EMASB(ram_dp_cfg_register[0]),
.TENA(1'b1),
.TCENA(1'b1),
.TWENA(1'b1),
.TAA(12'b0),
.TDA(32'b0),
.TENB(1'b1),
.TCENB(1'b1),
.TWENB(1'b1),
.TAB(12'b0),
.TDB(32'b0),
.RET1N(1'b1),
.SIA(2'b1),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b1),
.SEB(1'b0),
.COLLDISN(1'b1) 
);

endmodule
